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NetFPGA incorrect Ethernet PHY pins

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  • NetFPGA incorrect Ethernet PHY pins


    I am working on NetFPGA - 1G CML board with Kintex-7 FPGA (xc7k325tffg676). The reference manual for the board specified a set of pin numbers for the 4 Ethernet PHYs on the board, which is shown in the image attached. However, when I synthesized and implemented a small test design which gives inputs to Ethernet Lite IP core to be transmitted across PHY, I got the following error during implementation:
    • [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets phy_tx_clk_IBUF] > phy_tx_clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y214 and phy_tx_clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

    On posting a query on Xilinx forums, I was told that pin E13 is not a clock pin, whereas in the manual it is mentioned as phy_tx_clk. I was also directed to this link, which gives the package pin specifications by xilinx. All clock inputs should be given on Clock Capable (CC) pins indicated by SRCC or MRCC. However none of the 4 PHY transmit clocks (B9,D14,J10,E13) are CC pins. I checked the board schematic, but it is the same as the reference manual.

    If anyone had come across a similar problem, I would be thankful for some help.