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want to simulate the reference router in ncverilog/vcs

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  • want to simulate the reference router in ncverilog/vcs

    Hi,

    This is Sagar, I am new to the group- just started understanding the netFPGA and trying to simulate the reference router design for further understanding.
    I am trying to simulate the design in ncverilog (cadence simulator). But, I think- we need to have the verilog files for the coregen modules, but- the database only contains the .xco files in synth library under each directory wherever coregen is used.
    1. Is it possible to get these files? Or were these files submitted somewhere from where I can pick up these?
    2. Is there any design documentation on the reference router design- ca you please point me to the documentation if you have any?

    Can you please respond to me when u get some time. Thanks in advance for your time.

    Regards,
    Sagar
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