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  • Noob problem in building projects.

    [I hope this isn't being sent to the wrong place, and that it isn't inappropriate. If so, please tell me where I should send it]

    I'm working on a modified special purpose router, based on NetFPGA 10G. I was given a blob of Verilog which another developer (now inaccessible) had apparently got to work; we have a working bitstream from his time, but my task is to reproduce it so we can continue development. I'm pretty new to FPGAs.

    I've got ISE 13.4 installed (the same as the original developer used), along with the proper licenses. I have the latest NetFPA-10G. I can build pcores, and can proceed to a bitstream on the reference_flash project.

    However, I'm stymied on building my code. We're using a Makefile identical to the contrib/ported_router_oped_10g project.

    The early stages of 'make exporttosdk' work fine, but when it gets to the later stages, it complains of missing two files:

    Axi_interconnect_0_wrapper_xst.prj
    Nf10_oped_0_wrapper_xst.prj

    ...and can't proceed further.

    Prj files are included with the contrib and std pcores, but not with the cores in /xilinx. Its not clear to me what generates them.

    Noting that the reference_flash and reference_nic projects actually create a Axi_interconnect_0_wrapper_xst.prj file, out of curiosity I copied that to my project's synthesis directory (yes, I know it's almost certainly unsuitable), and retried the build - it got a little further, then complained of a missing Verilog file. I noted that the prj file had been copied to axi_interconnect_memory_mapped_lite_0_wrapper_xst. prj.

    The latter file is mentioned in synthesis.sh. I tried running the build in that script (xst -ifn <filename>), and to my surprise, found that the Verilog files it tried to build included Verilog keywords that it did not know how to parse (eg: 'localparam' inside a block).

    Then, since they had the same makefiles, I thought I'd build the ported_router_oped_10g project; it might make the missing files (and support four ports, unlike the reference_nic and flash projects). That failed early, missing a number of 'f1g*' port files.

    Thinking these must be in the NefFPGA 1G project, I downloaded and installed that, but unfortunately I can't build, lacking root on the build machine for the moment.

    OK, I realize the above is a bit of a rambling mess, but can anyone at least clear up for me how to get the two prj files I need (along with their Verilog partners)?

    Thanks in advance

    Peter Trei
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